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ILX505A
2592-pixel CCD Linear Image Sensor (B/W) For the availability of this product, please contact the sales office.
Description The ILX505A is a reduction type CCD linear sensor designed for facsimile, image scanner and OCR use. This sensor reads A3 size documents at a density of 200 DPI (Dot Per Inch). A built-in timing generator and clock-drivers ensure direct drive at 5V logic for easy use. Features * Number of effective pixels: 2592 pixels * Pixel size: 11m x 11m (11m pitch) * Built-in timing generator and clock-drivers * Ultra low lag * High sensitivity * Maximum clock frequency: 5MHz Absolute Maximum Ratings * Supply voltage VDD1 VDD2 * Operating temperature * Storage temperature Pin Configuration (Top View) 22 pin DIP (Ceramic)
11 6 -10 to +55 -30 to +80
V V C C
VOUT GND GND SHSW CLK VDD1 GND VDD2 T1
1 2 3 4 5 6 7 8 9
1
22 VDD2 21 NC 20 VDD1 19 RSSW 18 VGG 17 GND 16 GND 15 VDD1 14 NC 13 NC
EXRS 10 ROG 11 2592
12 GND
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E92Y22D78-PS
Block Diagram
NC
VDD1
NC
VDD2
GND
VDD1
GND
NC
22 20
21
17 16
15
14
13 12
S1
S2
D34
D35
GND
D15
D14
D33
VOUT CCD analog shift register
1
Read out gate
Output amplifier Sample-and-hold circuit
VGG 18
Clock-drivers
Clock pulse generator Sample-and-hold pulse generator
Mode selector
S2591
S2592
D36
D37
D38
Read out gate pulse generator
2 7
3
6 8 9 5
19
10
4
D39
11
VDD1
GND
GND
GND
VDD2
T1
CLK
EXRS
RSSW
SHSW
ROG
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ILX505A
ILX505A
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Symbol VOUT GND GND SHSW CLK VDD1 GND VDD2 T1 EXRS ROG GND NC NC VDD1 GND GND VGG RSSW VDD1 NC VDD2 Signal output GND GND Switch Description
{
with S/H GND without S/H VDD2
Clock pulse 9V power supply GND 5V power supply Test pin (VDD2) External RS pulse input. Must be connected to VDD2 when the internal RS pulse is used. Clock pulse GND NC NC 9V power supply GND GND Output circuit gate bias Reset pulse switchover pin 9V power supply NC 5V power supply
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ILX505A
Mode Description Mode in Use Internal RS Externel RS 19 pin RSSW 10 pin EXRS GND VDD2 VDD2 RS
Note) When the external RS mode is in use, operation of use internal S/H is not guaranteed. Pin 4 must be connected to 5V DC power supply.
Recommended Voltage Item VDD1 VDD2 Min. 8.5 4.75 Typ. 9.0 5.0 Max. 9.5 5.25 Unit V V
Note) Rules for raising and lowering power supply voltage To raise power supply voltage, first raise VDD1 (9V) and then VDD2 (5V). To lower voltage, first lower VDD2 (5V) and then VDD1 (9V).
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ILX505A
Electro-optical Characteristics (Ta = 25C, VDD1 = 9V, VDD2 = 5V, Clock frequency: 1MHz, Light source = 3200K, IR cut filter: CM-500S (t = 1.0mm)), When Internal RS (Pin 19 = GND, Pin 10 = VDD2) Item Sensitivity 1 Sensitivity 2 Sensitivity nonuniformity Saturation output voltage Dark voltage average Dark signal nonuniformity Image lag Dynamic range Saturation exposure 9V supply current 5V supply current Total transfer efficiency Output impedance Offset level Symbol R1 R2 PRNU VSAT VDRK DSNU IL DR SE IVDD1 IVDD2 TTE ZO VOS Min. 16.8 -- -- 1.5 -- -- -- -- -- -- -- 92.0 -- -- Typ. 21 53 2.0 1.8 0.3 0.5 0.02 6000 0.085 14.0 5.0 97.0 600 4.5 Max. 25.2 -- 8.0 -- 2.0 3.0 -- -- -- 20.0 10.0 -- -- -- Unit V/(lx * s) V/(lx * s) % V mV mV % -- lx * s mA mA % V Remarks Note 1 Note 2 Note 3 -- Note 4 Note 4 Note 5 Note 6 Note 7 -- -- -- -- Note 8
Notes) 1) For the sensitivity test light is applied with a uniform intensity of illumination. 2) W lamp (2854K) 3) PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 1. PRNU = (VMAX - VMIN)/2 x 100 [%] VAVE
The maximum output of all the valid pixels is set to VMAX, the minimum output to VMIN and the average output to VAVE. 4) Integration time is 10ms. 5) VOUT = 500mV 6) DR = VSAT/VDRK 7) SE = VSAT/R1 8) VOS is defined as indicated below. Signal is observed at PNP-type emitter follower out.
D31 OS D32 D33 S1
VOS
GND
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Clock Timing Diagram (For internal RS mode)
5
ROG
0
2 3 4
2631
1
5
CLK
0
D1
1
VOUT
D2 D3 D4 D5 D6
Dummy signal (33 pixels)
D11 D12 D13 D14 D15
Optical black (18 pixels)
D31 D32 D33 S1 S2 S3 S4
Effective picture elements signal (2592 pixels)
1-line output period (2631 pixels)
S2589 S2590 S2591 S2592 D34 D35 D36 D37 D38 D39
Dummy signal (6 pixels)
Internal S/H is not in use ILX505A
2
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Clock Timing Diagram (For external RS mode)
5
ROG
0
2 3 4
2631
1
5
CLK
0
5
RS
0
1
VOUT
D2 D3 D4 D5 D6
Dummy signal (33 pixels)
D11 D12 D13 D14 D15
Optical black (18 pixels)
D31 D32 D33 S1 S2 S3 S4
Effective picture elements signal (2592 pixels)
1-line output period (2631 pixels)
S2589 S2590 S2591 S2592 D34 D35 D36 D37 D38 D39
Dummy signal (6 pixels)
2
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ILX505A
ILX505A
CLK, VOUT Timing (For internal RS mode)
t1 t2
CLK t3 t4
t10
VOUT
t17
Item CLK pulse rise/fall time CLK pulse duty1 CLK - VOUT 1 CLK - VOUT 2 1 100 x t3/(t3 + t4)
Symbol t1, t2 -- t10 t17
Min. 0 40 50 30
Typ. 10 50 80 75
Max. -- 60 110 120
Unit ns % ns ns
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ILX505A
CLK, RS, VOUT Timing (For external RS mode)
t1 t2
CLK t3 t5 t4
RS t8 t6 t11 t9 t7 t10
VOUT
Item CLK, RS pulse rise/fall time CLK pulse duty1 CLK - RS pulse timing CLK - RS pulse timing RS pulse period CLK - VOUT RS - VOUT 1 100 x t3/(t3 + t4)
Symbol t1, t2, t8, t9 -- t6 t7 t5 t10 t11
Min. 0 40 0 50 50 50 30
Typ. 10 50 100 100 100 80 50
Max. -- 60 -- -- -- 110 70
Unit ns % ns ns ns ns ns
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ILX505A
ROG, CLK Timing
ROG
t13
t14
t15
CLK t12 t16
Item ROG, CLK pulse timing ROG pulse rise/fall time ROG pulse period
Symbol t12, t16 t13, t15 t14
Min. 500 0 500
Typ. 1000 10 1000
Max. -- -- --
Unit ns ns ns
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ILX505A
Example of Representative Characteristics
Spectral sensitivity characteristics (Standard characteristics)
10 Ta = 25C 9 8
Relative sensitivity
7 6 5 4 3 2 1 0 400 500 600 700 800 Wavelength [nm] 900 1000
MTF of main scanning direction (Standard characteristics)
0 1.0 Spatial frequency [cycles/mm] 9.1 18.2 27.3 36.4 45.5 1.0 0
MTF of sub scanning direction (Standard characteristics)
Spatial frequency [cycles/mm] 9.1 18.2 27.3 36.4 45.5
= 560nm
= 560nm
0.8
0.8
X-MTF
0.4
Y-MTF
0
0.6
0.6
0.4
0.2
0.2
0 0.2 0.4 0.6 0.8 Normalized spatial frequency 1.0
0 0 0.2 0.4 0.6 0.8 Normalized spatial frequency 1.0
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ILX505A
Application Circuit
5V
9V
10 10 1000p 22 (D) 1000p 21 20 (A) 19 (A) 18 (A) 10 17 (A) 16 (A) 15 (A) 14 (D) 13 (D) 12 (D) 1000p 10
(A) 1 9V 3k VOUT 100
(D) 2
(A) 3
(A) 4 5
(A) 6 1000p
(D) 7
(D) 8
(D) 9
(D) 10 11
10
10 1000p
2SA1175
CLK
5V
ROG
* Internal S/H is in use. Pin 4 must be connected to 5V DC power supply when S/H is not used. * Internal RS mode is used. For the external RS mode, connect Pin 19 and Pin 4 to 5V DC power supply and input a proper clock pulse into Pin 10. * When noise influence into output signal is large, connect pins indicated by (A) to the analog power supply and pins indicated by (D) to the digital power supply, and also use a decoupling capacitor of large capacitance.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
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ILX505A
Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Regulation for raising and lowering the power supply voltage When raising the supply voltage, first raise VDD1 (9V) and then VDD2 (5V). Similarly, lower VDD2 (5V) first and then VDD1 (9V). 3) Soldering a) Make sure the package temperature does not exceed 80C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. 4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.
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Package Outline
Unit: mm
22pin DIP (400mil)
41.6 0.5 28.512 (11m X 2592Pixels) 12
22
5.0 0.5
1 40.2
11
1. The height from the bottom to the sensor surface is 1.61 0.3mm. 2. The thickness of the cover glass is 0.7mm, and the refractive index is 1.5.
4.0 0.5
2.54
0.51
2.6 3.3 0.5
0.3
M
PACKAGE STRUCTURE
PACKAGE MATERIAL
Cer-DIP
LEAD TREATMENT
TIN PLATING
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
3.9g
(AT STAND OFF) 10.16
H
0.25
V No.1 Pixel
9.0 10.0 0.5
0 to 9
7.6 0.8
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ILX505A

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